1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same. In particular, the present invention relates to a technique effective in applying in a formation process of a capacitor element that is formed integrated with a transistor and a resistance element on a substrate.
2. Description of the Related Art
For instance, in patent literatures 1, 2, 3 and 4, a technique in which an HBT (Hetero-junction Bipolar Transistor), a resistance element and a capacitor element are formed on the same substrate is disclosed.
Patent literature 1: JP-A No. 2001-77204
Patent literature 2: JP-A No. 2001-326284
Patent literature 3: JP-A No. 2001-156179 and
Patent literature 4: JP-A No. 2002-252344
An HBT is considered being studied for use in a high-output power amplifier as a high-output power device capable of operating under a single power supply. In addition, since the HBT has the characteristics of being capable of being operated with high efficiency, etc., a technique for applying in a mobile communication device such as a portable telephone is under consideration. In the case of the HBT being applied to the mobile communication device, not only making the performance of the HBT element higher, but also miniaturizing a semiconductor chip (hereinafter simply referred to as chip) on which the HBT is formed, and forming a passive element such as a resistance element or a capacitor element and the HBT in the same chip are demanded.
The present inventors are studying an HBT that is used in a high-frequency module contained in a mobile communication device and also studying a technique of forming the HBT together with passive elements such as a resistance element and a capacitor element in one chip. In the course, the inventors found problems mentioned below. These problems will be explained with reference to FIGS. 39 and 40.
FIG. 39 is an essential sectional view of one example of a chip that the inventors have studied. Although in the chip, an HBT and passive elements such as a resistance element and a capacitor element are formed, in FIG. 39 a cross section of a capacitor element is illustrated. A process that forms a capacitor element in a chip and was studied by the inventors is as follows. On an insulating film 102 that is deposited on a semi-insulating substrate (hereinafter simply referred to as a substrate) 101 that has, for instance, GaAs (gallium arsenide) as a main component, a metal film 103 is formed and the metal film 103 is patterned. Subsequently, after on the substrate 101, an interlayer insulating film 104 that covers the metal film 103 is deposited, an opening 105 that reaches the metal film 103 is formed in the interlayer insulating film 104. In the next place, after an insulating film 106 is deposited on the interlayer insulating film 104 including the inside of the opening 105 thereof, the insulating film 106 is patterned. Subsequently, after a metal film 107 is deposited on the substrate 101, the metal film 107 is patterned. Thereby, a capacitor element C11 is formed in which the metal film 103 is a lower electrode, the insulating film 106 is a capacitor insulating film and the metal film 107 is an upper electrode. The inventors found that when a capacitor element C11 is formed according to such a process, the insulating film 106 bends in a lower region 105A of a sidewall of the opening 105 and a film thickness becomes thinner than other regions or film quality is deteriorated. When the film thickness of the insulating film 106 becomes thinner, the withstand voltage of the capacitor element C11 is deteriorated in the lower region 105A; accordingly, there is a problem in that a measure of improving a capacitance density of the capacitor element C11 by thinning a film thickness of the insulating film 106 cannot be taken. Furthermore, depending on the deposition conditions of an insulating film, an insulating film can be formed without reducing a film thickness in the lower region 105A. However, even in such cases, often times deterioration of film quality is caused. That is, owing to the deterioration of the film quality, a phenomenon that the withstand voltage at the region 105A deteriorates to not more than half of the withstand voltage at a planar portion is likely to occur. This is because although a plasma CVD (Chemical Vapor Deposition) device or the like is used to form an insulating film, the film quality and a film thickness at a stepped portion can be controlled with more difficulty in comparison with that in a planar portion. Furthermore, when the capacitor element C11 is formed, a process of forming the opening 105 and a process of patterning the insulating film 106 are necessary. Accordingly, there is another problem in that the number of processes for manufacturing a chip increases.
FIG. 40 is an essential sectional view of another example of a chip that the inventors studied. Also, in a chip shown in FIG. 40, similarly to the chip shown in FIG. 39, an HBT and passive elements such as a resistance element and a capacitor element are formed. However, in FIG. 40, a sectional view of a capacitor element is illustrated. A process that forms a capacitor element in the chip and was studied by the inventors is same as that for the chip explained with FIG. 39 up to a process of patterning the metal film 103. Thereafter, an insulating film 106 is deposited on a substrate 101. Subsequently, after a metal film 107 is deposited on the insulating film 106, the metal film 107 is patterned. Thereby, a capacitor element C11 is formed in which the metal film 103 is a lower electrode, the insulating film 106 is a capacitor insulating film and the metal film 107 is an upper electrode. In the example shown in FIG. 40, the insulating film 106 combines with an interlayer insulating film as well. The inventors found that when a capacitor element C11 is formed according to a process like this, in a region 103A of a sidewall lower portion of the metal film 103, a sidewall portion and a region up to a region 103B of a sidewall upper portion, a film thickness of the insulating film 106 becomes thinner than other regions or film quality is likely to deteriorate. Thus, when, in depositing the insulating film 106, the insulating film 106 becomes partially thinner or the film quality deteriorates, similarly to an example shown in FIG. 37, there is a problem in that a measure of improving the capacitance density of the capacitor C11 by thinning a film thickness of the insulating film 106 can be taken with difficulty.
An object of the present invention is to provide a technology that can improve the capacitance density while securing the withstand voltage of a capacitor element.
The above-mentioned and other objects and novel characteristics according to the present invention will be clarified from descriptions in the present specification and attached drawings.